Within a microprocessor-based computer system, locations in RAM and ROM/PROM memories and, in some systems, I/O devices are allocated permanent, physical addresses which are used by the system microprocessor to access memory or I/O locations during read or write operations. However, most computer processes or programs utilize; a logical or virtual addressing system to address system memory. A logical address is an address expressed as a location relative to a beginning or base location for a process, thus a process does not require use of the same physical memory addresses each time it executes. The size of the logical address space can be smaller than, equal to, or larger than the size of the physical address space. Logical memory having an address space which can be resigned to or translated physical memory is known as virtual memory.
Most microprocessors in use today support virtual addressing and also provide the capability of developing multitasking, multiuser, and distributed processing systems. These advanced features are supported through a hardware device known as a memory management unit, abbreviated as MMU. The MMU may be included on the same integrated circuit as the rest of the microprocessor, such as in the Intel 80386, 80486 and Pentium, the Motorola 68030 and 68040, and MIPS R2000/R3000 processors, or may be in a companion chip to the microprocessor, such as the 68851 paged MMU which accompanies the Motorola 68020 processor.
Memory management units generally provide the following functionality:
Support for dynamic memory allocation, providing for the efficient management of the physical address space; PA1 Support for virtual memory implementation, providing for the management of the virtual address space; PA1 Mapping of virtual addresses to physical addresses; PA1 Memory protection and task security (in some cases); PA1 Processing of page faults or bus fault exceptions, wherein addressed code or data not currently resident in main memory is called into memory and the associated page table is updated to allow task execution to complete; and PA1 Supporting sharing of code and data in main memory by multiple processes.
As indicated above, one of the primary functions of an MMU is to receive virtual addresses and map them into physical addresses. Several mapping techniques are commonly employed, such as paging, segmentation, and segmented paging.
Paging, possibly the most widely supported mapping technique, involves the partitioning of memory into equal fixed-size chunks known as frames, and the division of each process into the same size chunks known as pages. Pages are allocated to frames which are distributed throughout the memory. In order to keep track of the physical location of each memory page, the operating system maintains a page table. The page table includes a number of entries, referred to as page table entries, each of which shows the frame location for each page of a process. Each process operates with logical addresses which include a page number and relative address within the page. In order to access a memory page, the page number is used to address an entry in the page table in order to obtain the frame location.
In a virtual memory implementation, it is not necessary that an entire task be placed into main memory for execution. Generally, only a small number of pages or segments (discussed below) for a task need be resident in main memory at any moment. When the system encounters a portion of a task not resident in memory, the mapping mechanism will generate a high priority exception referred to as a page fault, bus error exception or segment-not-present exception). The operating system is responsive to this page fault to find the required page or segment in secondary storage and move the page or segment into main memory. As task execution progresses, additional pages or segments will be called into main memory as required, replacing pages or segments not currently needed, to permit the task to complete.
In a paged mapping system, the operating system must maintain a page table for each active task or process. One disadvantage of a paged mapping system is that the size of the page tables can become quite large.
When multiple processes are active, a significant amount of main memory may be occupied by page tables.
Segmentation is another way in which memory can be subdivided. In a segmented system, the programmer or compiler subdivides a task's logical address space into modules of varying sizes identified as segments, each segment being addressed by a segment number. A segment comprises a block of contiguous locations within the logical address space, which is placed in its whole into main memory when required during task execution. Segments are of large size than data pages; but like data pages, segments are located by means of a entries in a segment table, the segment table entries having data access bits associated therewith.
Because of the larger size of segments versus pages, and further because the size of segments may vary, memory fragmentation problems can occur. Fragmentation results form the swapping of segments into an out off memory creates large gaps in system memory between areas occupied by active segments, the gaps not containing enough contiguous locations to accommodate all segments which may be called into main memory.
Although paging alone, and segmentation alone, each have weaknesses, the two concepts can be combined to produce a mapping system which minimizes these weaknesses while obtaining some of the advantages of both paging and segmentation. In a segmented-paging system, a task's logical address space is divided into segments, and each segment is partitioned further into pages of equal size. Main memory is also partitioned into page frames of equal size. Utilizing this scheme, the pages of a segment placed into main memory need not occupy contiguous locations within main memory. A segmented-paging scheme requires the operating system to maintain both a segment table as well as a page table, and two levels of translations are required to compute a physical address.
It should be noted that many improvements and modifications to the mapping schemes summarized above are possible. Unique mapping schemes may be developed to produce optimal performance for specific applications or systems. Many of these mapping schemes can be implemented in software as well as in MMU hardware. It should also be noted that the MMUs incorporated into or utilized with many popular microprocessors which support virtual addressing limit the virtual and physical address space to four gigabytes. Thus a memory management system supporting virtual address spaces greater than four gigabytes, and providing optimal memory performance for differing applications is desired.